Generally, a semiconductor integrated circuit requires high circuit performance and high density. Therefore, in the case of a metal oxide semiconductor field effect transistor (or "MOSFET"), the technology for the forming a semiconductor integrated circuit has been scaled down to a sub-micron range as a result of the efforts to reduce the size of the device. Only through a reduction of the horizontal dimension and a proportionate reduction of the vertical dimension, can a functional equilibrium between various devices be achieved. That is, if the distance between the source and drain is reduced as a result of the reduction of the size of the device, an undesirable variation of the characteristics of the device occurs, a typical example being the short channel effect. If this short channel effect is to be overcome, a horizontal scale-down has to be carried out; that is, the gate length has to be reduced. Further, a vertical scale-down has to be carried out; that is, the thickness of the gate insulation dielectrics and the depth of the junction and the like have to be reduced. Further, the applied voltage has to be lowered, and the doping concentration of the semiconductor substrate has to be increased. Particularly, the doping profile for the ion implantation depth of the channel region has to be controlled. The applied voltage for the semiconductor device, however, has to satisfy the power source for the electronic apparatus in which the semiconductor device is used. Therefore, while the dimension of the semiconductor device is scaled down, the electrical dimension for the applied power source of the circuit is not reduced. In the case of a MOS device, particularly in the case of an NMOS transistor, the distance between the source and drain is reduced as a result of the reduction of the channel. Accordingly, the electrons which are supplied from the source are abruptly accelerated by a high electric field near a pinch-off region near the channel of the drain junction, thereby producing hot carriers. Thus, the NMOS transistor is vulnerable to these hot carriers. (Refer to Chenming Huet et al, "Hot-electron-induced MOSFET Degradation-Motel, Monitor and Improvement", IEEE Transactions on Electron Devices, Vol. ED-32, No. 2, February 1985, pp. 375-385).
According to the above cited paper, the instability of hot carriers is caused by a high electric field near the drain junction, which is caused by the short channel length and the high applied voltage. Hot carriers thus generated are injected into the gate insulating layer, which can result in substrate current. Therefore, an LDD (lightly doped drain) structure was proposed in 1978, which improves the NMOS device which is subject to hot carriers and has a reduced channel length. (Refer to K. Saito et al, "A New Short Channel MOSFET with Lightly Doped Drain", denshi tsushin rengo taikai (in Japanese), April 1978, p. 220).
The LDD structure has characteristics such that the side length is narrow, and a self-aligned lightly doped n.sup.- region is disposed between the channel and the highly doped n.sup.+ source/drain region. This n.sup.- lightly doped region spreads out the high electric field near the drain junction, so that carrier electrons supplied from the source are not abruptly accelerated, thereby overcoming the current instability due to hot carriers. Since studies on semiconductor devices of over 1 mega-bit DRAMs have begun, techniques for manufacturing MOSFETs having an LDD structure have been proposed in various forms. Of them, the most typical one is that in which the LDD is formed by providing a side wall spacer on each of the side walls of the gate, and this technique is being used in most mass production devices.
FIG. 1 illustrates a conventional process for forming an NMOS transistor having an LDD structure.
First referring to FIG. 1A, active region 10a and isolated region 10b are formed upon silicon substrate 10. Gate insulating layer 12 is formed on the surface, and polysilicon layer 13' is formed thereupon. Cap gate oxide layer 14' is formed on polysilicon layer 13'.
As illustrated in FIG. 1B, cap gate oxide layer 14' and polysilicon layer 13' are etched by applying a photo etching method, thereby forming gate (electrode) 13 over which is oxide layer 14.
As illustrated in FIG. 1C, an ion-implantation (phosphorus ion) is carried out on the whole surface with a light dose and with a low implanting energy to form n.sup.- region 101.
As illustrated in FIG. 1D, silicon oxide layer 15 is deposited on the whole surface by applying a chemical vapor deposition method (CVD) in order to form side wall spacers.
Thereafter, as illustrated in FIG. 1E, the whole surface is etched back by applying a reactive ion etching (RIE) process so that a part of silicon oxide layer 15 remains on the side faces of cap gate oxide layer 14 and gate 13. In this process, gate insulating layer 12 which is not protected by the gate also is etched, thereby exposing the surface of the silicon substrate. Thus, side wall spacer 15' consisting of a part of silicon oxide layer 15 and a part of gate insulating layer 12 is formed on the side walls of cap gate oxide layer 14 and gate 13.
Thereafter, as illustrated in FIG. 1F, an n-type dopant ion implantation is carried out with a large dose, thereby forming source/drain region 102 doped (n.sup.+) with a high concentration and having a deep junction. Under this condition, gate side wall spacer 15' plays the role of a barrier during the high concentration ion implantation for forming the source/drain region. Therefore, n.sup.- junction 101', which is not affected by the high concentration doping, if formed between channel C of the gate and source/drain region 102. (Refer to Paul J. Tsang et al, "Fabrication of High Performance LDDFET's with Oxide Sidewall-Spacer Technology" IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April 1982).
There are, however, several problems in forming LDD devices by providing gate side wall spacers. Particularly, this technology is not suitable for future formation of semiconductor devices requiring high density and high prestige.
In this technique, in order to form a gate side wall spacer, deposition of an oxide is carried out by applying a CVD method, followed by an etch-back. Therefore, during this etching, the active region of the silicon substrate is exposed, and contaminated. Further, the active region of the silicon substrate is over-etched, thereby damaging the silicon substrate. Further, the over-etched depth is not uniform over the positions of the silicon wafer in accordance with the density of the patterns and, therefore, the electrical characteristics of the semiconductor device become non-uniform.
That is, as illustrated in FIG. 2, plasma radical species such as CF3, CHF3 and O.sub.2 used during the etching of the oxide layer intrude into the silicon substrate. Therefore, although varying depending on the RF power during etching, a compound layer of about 500 .ANG. is formed, the compounds including CF.sub.x - polymers, Si--C, Si--O, Si--O--C.
FIG. 2 is a graphical illustration of the results of analysis using a secondary ion mass spectroscopy (SIMS) for the case where the plasma radical species intrude into the silicon substrate to contaminate the substrate during the etching of the oxide layer by using CF3, CHF3, O.sub.2 and the like based on the conventional technique.
In the graph, the X axis illustrates the depth from the silicon surface, i.e., the value of the projection range as against the sputtering time, while the Y axis illustrates the concentration without unit in relative terms and in a logarithmic value. As can be seen from the graph, the concentrations of fluorine, oxygen and carbon near the surface of the silicon are higher than the concentration of the silicon and, therefore, these elements form a compound layer of about 500 .ANG. from the surface, the compounds being such as CF.sub.x -polymers, Si--C, Si--O, and Si--O--C.
In high density devices requiring a shallow junction, the bonding sites of the above-mentioned compounds exist within a depletion region when power is applied to the junction. Therefore, such bonding sites serve the role of a trap center for generating carriers, resulting in an increase in junction leakage current.
These findings are disclosed in Jeong Kim et al., "Cleaning Process for Removing of Oxide Etch Residue," Proceedings of Contamination Control and Defect Reduction in Semiconductor Manufacturing I, pp. 408-415, 1992, Toronto, and are summarized in FIG. 3 and FIG. 4 (table 4.)
FIG. 3 is a graphical illustration of the variation of the lifetime of minority carriers (a time during which the minority carriers exist in silicon) according to etch processes of the side wall oxide. As illustrated in FIG. 3, the lifetime of the minority carriers are recovered to the original state of the silicon wafer, that is, about 100 .mu.s, similar to the value before etching it. In FIG. 3, the "a" point indicates a lifetime (minority carrier lifetime) in the raw wafer itself (substrate) prior to etching the oxide side wall process. The "d" point indicates a lifetime in the wafer after etching the oxide side wall process by an RIE (reactive ion etch), thus receiving damage. The "b" point indicates a lifetime in the wafer in which the damaged portion is removed by an RIE process. The "c" point indicates a lifetime in the wafer in which the damaged portion is removed by a CDE (low damage Chemical Dry Si substrate Etch) process. The minority carrier lifetime is reduced to about 10 .mu.s ("d" point) just after the etch of the oxide to form the side wall spacer. The damaged substrate is restored to over 100 .mu.s ("c" point) by carrying out a low damage chemical dry etch. Further, if the damaged substrate is removed by a reactive ion etch (RIE), then the lifetime is improved to over 50 .mu.s ("b" point). That is, if the damaged or contaminated portions are removed, the quality of the silicon substrate is restored to the original level.
FIG. 4 illustrates the dependence of junction leakage current on cleaning methods during formation of the gate side wall spacer. As can be seen from FIG. 4, if the silicon substrate is excessively etched, the damaged region increases, and, therefore, junction leakage also increases. If the etch-damaged or contaminated portions are removed, however, the junction characteristics are improved. In other words, in conventional technology in order to make the junction area beside the gate side wall free from damage, an over etch and low damage chemical dry etch process is required.
There is another problem with the conventional technique. Junction leakages were caused by dislocation lines which are across the junction layer from the side wall edge in MOS devices with an LDD structure.
As illustrated in FIG. 5, the gate side wall spacer is generally formed almost vertical relative to the silicon substrate and, therefore, the stress is concentrated on the corner where the side wall spacer meets the silicon substrate. Therefore, as indicated by dislocation line 555, which is formed from the corner of the spacer to the bulk of the substrate, a crystal defect is formed. This dislocation line increases the leakage current of the junction, and the data retention property is aggravated.
FIG. 5 is a sectional view of a MOSFET having an LDD structure and a silicon dioxide gate side wall spacer in the conventional semiconductor device.
Dislocation loops 500 and 501 which are formed during an As.sup.+ ion implantation and subsequent annealing appear on silicon substrate 50 in the form of a loop. Crystal defect 500 of the upper layer is positioned at the depth center R.sub.p of the impurity ions, while crystal defect 501 of the lower layer is positioned at a boundary depth between the non-crystalline and crystalline portions. Particularly, stress generated by differences in thermal properties is concentrated on the corners of side wall spacer 55 of gate 53, with the result that a crystal defect is generated as indicated by dislocation line 555.
It is predicted that such a crystal defect is caused when the thermal stress becomes larger than the silicon bonding energy. Therefore, as illustrated in FIGS. 6A and 6B, the distribution of the stress becomes different in accordance with the shape of the gate side wall spacer.
FIGS. 6A and 6B illustrate the stress distribution from the gate side wall spacer to the silicon substrate of an NMOSFET having an LDD in a conventional semiconductor device.
Referring to FIG. 6A, a crystal defect in impurity diffusion layers 600 and 601 results from side wall spacer 65 due to the difference between the thermal expansion rates of silicon substrate 60 and gate side wall oxide layer 65. When the steeply shaped side wall is formed, the stress is concentrated at the side wall edge and indicates a value of about 5.4.times.10.sup.9 dyn/cm.sup.2. This stress exceeds the bonding energy of the crystal, thereby leading to defect "S" in FIG. 6A. That is, the magnitude of the stress becomes larger than the silicon bonding energy, with the result that dislocation "S" occurs.
Referring to FIG. 6B, if the side wall spacer is less steeply shaped, the stress is concentrated at the side wall edge and indicates a value of about 2.7.times.10.sup.9 dyn/cm.sup.2. Thus a defect depicted "S'" in FIG. 6B occurs only a little. Here also side wall spacer 65' at gate 63' affects diffusion layers 600' and 601' due to thermal expansion differences between silicon substrate 60' and gate side wall oxide layer 65'.
In short, the stress imposed on the silicon substrate is varied within the range of about 2.7.times.10.sup.9 -5.4.times.10.sup.9 dyn/cm.sup.2 in accordance with the shape of the gate side wall spacer and the angle between the spacer and the substrate. The steeper the side wall spacer relative to the substrate, the more frequent the crystal defect, i.e., the more frequent the dislocation. (Refer to Shigeo Onishi et al., "Formation of a Defect Free Junction Layer by Controlling Defects Due to As.sup.+ Implantation" IEEE/ERPS, 1991, pp. 255-259.)
FIG. 8 is a graphical illustration of the junction leakage current versus dislocation depth in the side wall spacer.
The X axis illustrates the depth of the dislocation line based on the profile of the conventional gate side wall spacer, while the Y axis illustrates the magnitude of the leakage current. It is seen that the greater the steepness of the side wall spacer, the greater the leakage current.
As the size of the device is scaled down, the acceptable tolerance is reduced. Therefore, there are still unsolved problems in that plasma species intrude into the substrate during deposition of the oxide layer based on a CVD process (which is the critical step in the formation of the gate side wall spacer), and during the etching due to the over-etch. Another problem is the degradation of the device characteristics (such as leakage current at the junction layer) due to the crystal defect such as dislocations attributed to the profile of the side wall spacer. Therefore, a study is being carried out for improving the manufacturing process for an LDD device utilizing a conventional side wall spacer.
Also another study is being carried out for obtaining a solution to the problems of forming an LDD device utilizing the side wall spacer based on a substitution method.
FIGS. 7A to 7C illustrate an improvement of the conventional technique of forming an LDD transistor by adding an etch stop layer and utilizing a side wall spacer.
As illustrated, gate 73 is patterned, and etch stop layer 777 (polysilicon or Si3N4) is formed on gate insulating and pad oxide layer 72 to protect silicon substrate 70 during etch-back of CVD SiO.sub.2 for forming side wall spacer 75. Then CVD SiO.sub.2 75 is deposited and etched back, so that an excessive etch of the silicon substrate and contamination of the etchant with plasma species are prevented. In the last step illustrated in FIG. 7C, in order to form a highly doped impurity region n+, an ion implantation is carried out, after removing spacer 75.
This conventional technique, however, cannot give a solution to the problem of the defect of crystal dislocation which is caused by the profile of the side wall spacer.
Another method suggested in U.S. Pat. No. 4,599,118 is an overhang technique where a stacked structure of SiO.sub.2 /Si3N4/polysilicon/SiO.sub.2 is gate-patterned and the polysilicon is excessively etched, thereby forming an SiO.sub.2 /Si3N4 overhang. An As.sup.+ source/drain ion implantation is carried out using the overhang as an ion implantation mask, and the overhang is removed in order to carry out an n.sup.- ion implantation for forming an n.sup.- region.
In brief, the scaled-down transistors come to have short channels, with the result that hot carriers are produced, thereby raising the problem of hot carrier instability. In order to overcome this problem, a transistor having an LDD has been proposed, and in the practical fields, the LDD was formed utilizing a gate side wall spacer. In high density devices of over 16 mega-bit DRAMs, however, the LDD device formed by utilizing a side wall spacer has become unsuitable for the reasons cited above.